Data processing device and data processing system

ABSTRACT

A data processing device includes a first power-on reset circuit, a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit, a low voltage detect circuit, a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state, a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit, and a power supply node providing a power to the data processing device.

The present application is a Continuation Application of U.S. patentapplication Ser. No. 13/816,477, filed on Feb. 11, 2013, which is basedon International Application No. PCT/JP2010/064363, filed on Aug. 25,2010, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a data processing device, andparticularly to a data processing device having a central processingunit and to a data processing system in which the data processing deviceis used.

BACKGROUND ART

The electricity meter is one of the devices that have conventionallybeen passively controlled but recently been required to perform activecontrol using a data processing device including a central processingunit (CPU).

In the conventional electricity meter, the data processing device hasbeen required to perform the function of measuring and recording theconsumed amount of electric power generated by a power company andsupplied through a power grid to each house, as well as the function oftransmitting to the power company the recorded amount of powerconsumption through a predetermined communication line.

As for the electricity meter used for next-generation power grids, thedata processing device is required not only to perform processing formeasuring the amount of electric power distributed from the powercompany but also to perform processing such as processing for conductingreverse-power-flow control under which electric power from a powergeneration system such as photovoltaic cell or from a power storagesystem installed in each house is fed back to the power grid, as well asprocessing for offsetting the amount of distributed electric power andthe amount of electric power fed back to the power grid.

Even a system like the electricity meter is required to reduce as muchas possible the electric power consumed by the electricity meter itself.Regarding the data processing device performing the processing asdescribed above, the period during which the data processing device isin the standby state is relatively longer than the period during whichthe data processing device is performing processing. It is thereforenecessary to reduce not only the power consumption of the period duringwhich the data processing device is performing processing but also thepower consumption of the period during which the data processing deviceis in the standby state.

In order to minimize the power consumption of the data processing devicein the standby state, the data processing device in the standby state isswitched to a low power consumption state. For achieving this low powerconsumption state, it is necessary not only to stop supply of electricpower to functional units including the central processing unit (CPU)and stop an oscillator which generates an operation clock in the dataprocessing device, but also to reduce the power consumption of a powersupply circuit itself in the data processing device.

CITATION LIST Patent Literature

-   PTL 1: Japanese Patent Laying-Open No. 2008-040559-   PTL 2: Japanese Patent Laying-Open No. 2008-040543

SUMMARY OF INVENTION Technical Problem

Some of the data processing devices as described above have a Power-OnReset (POR) circuit for detecting a change of an externally suppliedpower supply voltage, from a voltage level immediately after the powersupply voltage is fed, to an operating voltage level and then perform apower-on reset operation in the data processing device. The POR circuitcompares the externally supplied power supply voltage with a referencevoltage. When the POR circuit detects that the externally supplied powersupply voltage has increased to a predetermined voltage level, the PORcircuit outputs a reset signal into the data processing device tothereby cause other circuits including the central processing unit (CPU)to be initialized.

The data processing devices also have an LVD (Low Voltage Detect)circuit. When the LVD circuit detects that the externally supplied powersupply voltage, on the contrary, has decreased to a predeterminedvoltage level, the LVD circuit issues, to the central processing unit(CPU), an interrupt signal or reset signal representing the decrease ofthe voltage, to thereby cause the central processing unit (CPU) toperform an appropriate operation for the decrease of the voltage or tobe initialized.

These POR circuit and LVD circuit include a reference voltage generationcircuit which uses a BGR (Band Gap Reference) circuit causing a certainamount of steady-state current to flow. The steady-state current is apart of the current consumed by the data processing device in the lowpower consumption state.

An object of the present invention is to provide a data processingdevice and a data processing system capable of reducing the currentconsumption in the standby state.

Solution to Problem

In summary, the present invention is a data processing device including:a first power-on reset circuit; a second power-on reset circuit withhigher power consumption and higher reset voltage accuracy than thefirst power-on reset circuit; a storage unit storing information fordetermining whether to keep the second power-on reset circuit in anactive state or an inactive state; and a central processing unitinitialized in response to respective outputs of the first and secondpower-on reset circuits and setting the information in the storage unit.

In another aspect, the present invention is a data processing systemincluding a printed circuit board and a data processing device mountedon the printed circuit board. The data processing device includes: afirst power-on reset circuit; a second power-on reset circuit withhigher power consumption and higher reset voltage accuracy than thefirst power-on reset circuit; a storage unit storing information fordetermining whether to keep the second power-on reset circuit in anactive state or an inactive state; and a central processing unitinitialized in response to respective outputs of the first and secondpower-on reset circuits and setting the information in the storage unit.

Advantageous Effects of Invention

In accordance with the present invention, the current consumption of thedata processing device and the data processing system in the standbystate can be reduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an example of the data processing systemhaving the data processing device.

FIG. 2 is a schematic configuration diagram of the data processingdevice having a central processing unit (CPU).

FIG. 3 is a block diagram showing a configuration of a voltage detectionunit and a power supply circuit.

FIG. 4 is a circuit diagram showing an example of a power-on resetcircuit PORa.

FIG. 5 is a circuit diagram showing an example of a power-on resetcircuit PORb and a low voltage detect circuit LVD.

FIG. 6 is a diagram for illustrating output characteristics of power-onreset circuit PORa.

FIG. 7 is a diagram for illustrating output characteristics of power-onreset circuit PORb.

FIG. 8 is a block diagram showing main brocks of the data processingdevice.

FIG. 9 is an operation waveform chart for illustrating a low powerconsumption period and an operation period.

FIG. 10 is a flowchart for illustrating a process regarding a power-onreset operation performed by the data processing device.

DESCRIPTION OF EMBODIMENTS

An embodiment of the present invention will hereinafter be described indetail with reference to the drawings. In the drawings, the same orcorresponding components are denoted by the same reference characters,and a description thereof will not be repeated.

Regarding the present embodiment, a description will be given of anexample where a first reset signal generation circuit with relativelylow power consumption and relatively low detection-voltage accuracy, anda second reset signal generation circuit with relatively high powerconsumption and relatively high detection-voltage accuracy are provided,and a user can select one of the first reset signal generation circuitand the second reset signal generation circuit to use.

FIG. 1 is a diagram showing an example of the data processing systemhaving the data processing device.

Referring to FIG. 1, a data processing system 1 includes a printedcircuit board 18, as well as a data processing device 2, a sensor 4, acommunication unit 6, a timer 8, and a battery 12 that are mounted onprinted circuit board 18. To data processing device 2, the voltage ofbattery 12 is supplied as power supply voltage Vcc.

FIG. 2 is a schematic configuration diagram of the data processingdevice having a central processing unit (CPU). FIG. 2 shows, in additionto components of a common microcomputer, functional units specific tothe present invention.

Referring to FIG. 2, data processing device 2 includes a centralprocessing unit CPU, a memory 22, a bus 21 transferring data andaddresses, a data transfer unit (Direct Memory Access Controller) DMAC,an analog-to-digital conversion unit ADC, an interrupt controller INTC,a serial communication unit SCIO, a system control unit SYSC, a clockcircuit 26, a power supply circuit 24, and a storage unit 28.

Central processing unit CPU successively executes programs stored inmemory 22 and controls the operation of data processing device 2 as awhole. Serial communication unit SCIO stores externally input data inmemory 22. Analog-to-digital conversion unit ADC converts an externallyinput analog signal to a digital value and stores the digital value inmemory 22. Data transfer unit DMAC controls data transfer through bus21, when serial communication unit SCIO or analog-to-digital conversionunit ADC stores digital data in memory 22.

Interrupt controller INTC receives an interrupt signal issued by anexternal or internal functional unit, and causes interruption to centralprocessing unit CPU. Central processing unit CPU performs processing inaccordance with the type of interruption. Clock circuit 26 generatesoperation clock CLK for data processing device 2 and supplies, to eachfunctional unit in data processing device 2, the operation clock of afrequency appropriate for the functional unit.

Referring to FIGS. 1 and 2, sensor 4 generates an analog signal to beinput to analog-to-digital conversion unit ADC. Communication unit 6controls data communication with devices external to the system, andinputs data to serial communication unit SCIO or receives data fromserial communication unit SCIO. Timer 8 issues an interrupt signal todata processing device 2, in accordance with passage of time which isset by data processing device 2. To data processing device 2, operatingpower supply voltage Vcc is supplied from the battery which isexternally connected to data processing device 2.

In the system having the above-described configuration, the degree ofbattery degradation (decrease of the electromotive force in the case ofthe primary battery, decrease of the current supply ability due todecrease of the power storage ability resultant from repeated chargingand discharging in the case of the secondary battery) influences theoperational stability of data processing device 2.

Power supply circuit 24 lowers or raises externally supplied powersupply voltage Vcc to generate internal operating voltage Vdd forexample, and supplies the generated voltage to the central processingunit (CPU) for example. A voltage detection unit 10 has power-on resetcircuits PORa and PORb generating a reset signal which triggers apower-on reset operation, in response to a voltage change of externallysupplied power supply voltage Vcc, and has a low voltage detect circuitLVD generating an interrupt signal or a reset signal in response to avoltage decrease of externally supplied power supply voltage Vcc.

Power-on reset circuit PORa is a voltage detection circuit with lowpower consumption and low detection accuracy, while power-on resetcircuit PORb is a voltage detection circuit with relatively higher powerconsumption and relatively higher detection accuracy than power-on resetcircuit PORa.

When power-on reset circuit PORa detects an increase of externallysupplied power supply voltage Vcc to a voltage for example in a range of2.0 V to 2.5 V (PORa's detection voltage Vrst (PORa)), power-on resetcircuit PORa cancels reset signal NPORA or, when power-on reset circuitPORa detects a decrease thereof to this voltage Vrst (PORa), power-onreset circuit PORa outputs reset signal NPORA.

When power-on reset circuit PORb detects an increase of externallysupplied power supply voltage Vcc to a voltage for example of 2.6 V±0.1V (PORb's detection voltage Vrst (PORb)), power-on reset circuit PORbcancels reset signal NPORB or, when power-on reset circuit PORb detectsa decrease thereof to this voltage Vrst (PORb), power-on reset circuitPORb outputs reset signal NPORB.

FIG. 3 is a block diagram showing a configuration of the voltagedetection unit and the power supply circuit.

Referring to FIG. 3, voltage detection unit 10 includes a current sourceCS, a band gap reference circuit BGR, a reference voltage generationcircuit VREFBUF, power-on reset circuits PORa, PORb, and a low voltagedetect circuit LVD.

Current source CS is a steady-state current source for generating biasvoltage Vbias and is always set in the ON state while data processingdevice 2 is powered. Band gap reference circuit BGR is a referencevoltage generation circuit with low voltage-dependency and lowtemperature-dependency. Reference voltage generation circuit VREFBUF isa reference voltage generation circuit which performs trimming based onreference voltage VrefI from band gap reference circuit BGR to generatedesired reference voltage VrefO.

For data processing device 2, a circuit system can be employed that cutsoff supply (stops supply) of the operating power supply voltage to apart or the whole of the internal circuitry upon transition to thestandby mode (low power consumption state), to thereby reduce thestandby current. For example, in a predetermined low power consumptionmode such as software standby mode, supply of the operating power supplyvoltage to an internal ROM which does not need supply of the operatingpower supply voltage may be cut off and, in another predetermined lowpower consumption mode such as deep standby mode, supply of theoperating power supply voltage to the whole or a part of internal logiccircuits such as CPU may be cut off, in addition of supply of thevoltage to the internal ROM. Furthermore, if it is unnecessary to holddata of a RAM, supply of the operating power supply voltage to the RAMmay also be cut off.

Power supply circuit 24 includes a plurality of voltage down convertersVDCs. Voltage down converter VDC is a circuit generating a power supplyvoltage for the internal circuitly of the chip, based on the referencevoltage from reference voltage generation circuit VREFBUF. In the lowpower consumption state (deep standby mode), voltage down converter VDCstops operating.

In a normal operation period, power-on reset circuits PORa and PORb areused. In a low power consumption period, stoppage of power-on resetcircuit PORb can be selected. This selection is made based on setting ofregisters in storage unit 28.

In the case where power-on reset circuit PORb and low voltage detectcircuit LVD are used, it is necessary that current source CS, band gapreference circuit BGR, and reference voltage generation circuit VREFBUFin FIG. 3 are operating. In contrast, in the case where only power-onreset circuit PORa is used while power-on reset circuit PORb and lowvoltage detect circuit LVD are not used, it is enough that only currentsource CS is operating. In a low power consumption period of the standbymode, power-on reset circuit PORb and low voltage detect circuit LVD canbe stopped to eliminate the current consumption of power-on resetcircuit PORb and low voltage detect circuit LVD. In addition, band gapreference circuit BGR and reference voltage generation circuit VREFBUFcan further be stopped to further eliminate the current consumption ofband gap reference circuit BGR and reference voltage generation circuitVREFBUF.

FIG. 4 is a circuit diagram showing an example of power-on reset circuitPORa.

FIG. 5 is a circuit diagram showing an example of power-on reset circuitPORb and low voltage detect circuit LVD.

Referring to FIG. 4, power-on reset circuit PORa includes a P channelMOS transistor 42 connected between a node to which power supply voltageVcc is supplied and a node N1 and having its gate to which a ground nodeis connected, a depression-type N channel MOS transistor 44 connectedbetween node N1 and the ground node, and a capacitor 46 connectedbetween node N1 and the ground node.

Power-on reset circuit PORa further includes inverters 48, 50 connectedin series to each other, having respective inputs connected to node N1,and outputting reset signal NPORA. Reset signal NPORA represents resetby its low level and represents cancellation of reset by its high level.

Referring to FIG. 5, current source CS, band gap reference circuit BGR,and reference voltage generation circuit VREFBUF are shared by power-onreset circuit PORb and low voltage detect circuit LVD. Voltage Vbiasgenerated by current source CS is supplied to band gap reference circuitBGR, reference voltage generation circuit VREFBUF, and voltagecomparators 58, 62.

Voltage comparator 58 has a positive input node receiving an output of avoltage dividing circuit 54, has a negative input node receiving anoutput of band gap reference circuit BGR, and compares them with eachother. Alternatively, as shown in FIG. 3, voltage comparator 58 may beconfigured to receive the output of reference voltage generation circuitVREFBUF instead of the output of band gap reference circuit BGR.

Voltage comparator 58 outputs reset signal NPORB. Reset signal NPORBrepresents reset by its low level and represents cancellation of resetby its high level.

A selector 56 selects one of a plurality of voltage fractions generatedby and output from voltage dividing circuit 54. A selector 60 selectsone of a plurality of outputs from reference voltage generation circuitVREFBUF. The output of selector 56 and the output of selector 60 areinput to voltage comparator 62. Voltage comparator 62 has its positiveinput node receiving the output of selector 56 and has its negativeinput node receiving the output of selector 60 to compare them with eachother. Voltage comparator 62 outputs reset signal NLVD. Reset signalNLVD represents reset by its low level and represents cancellation ofreset by its high level.

FIG. 6 is a diagram for illustrating output characteristics of power-onreset circuit PORa.

Referring to FIGS. 4 and 6, the threshold voltage of depression-type Nchannel MOS transistor 44 has a negative value and can therefore be madeelectrically conductive even when the power supply voltage is 0 V. Thus,when power supply voltage Vcc is 0 V, node N1 is kept at 0 V.Accordingly, node N1 can easily be initialized without using a passiveelement such as resistor.

After the power supply voltage is supplied, while gate-to-source voltageVgs of P channel MOS transistor 42 is equal to or lower than thethreshold voltage of P channel MOS transistor 42, node N1 is kept at 0V.

When externally supplied power supply voltage Vcc increases from 0 V tovoltage VLa at which inverters 48, 50 can operate, the output ofpower-on reset circuit PORa is fixed at a low level.

After this, when power supply voltage Vcc increases and the drivingability of transistor 42 becomes larger than the driving ability oftransistor 44, the potential of node N1 starts increasing. Then, whenthe potential of node N1 exceeds the threshold voltage of inverter 48,the output is reversed from the low level to a high level andaccordingly reset is cancelled.

This output becomes the high level which represents cancellation ofreset, when power supply voltage Vcc is in a range of 2.0 V to 2.5 V. Inthe current path of transistors 42, 44 in FIG. 4, steady-state currentflows to the ground node from the node to which power supply voltage Vccis supplied. This current is a small value for example of approximately0.1 μA. This steady-state current is chiefly determined depending on thedriving ability of transistor 44.

The dimensions of depression-type N channel MOS transistor 44 can beadjusted to reduce the steady-state current. Moreover, the ratio of thearea occupied by transistor 44 to the whole on-chip area is less thanthat of a resistor, and therefore use of transistor 44 is moreadvantageous also in terms of the cost.

Regarding power-on reset circuit PORa, however, reset cancellationvoltage VHa varies in the range of 2.0 V to 2.5 V. This is for thereason that variation of process parameters causes variation of thethreshold voltage of inverter 48 and the balance between respectivedriving abilities of transistors 42, 44.

FIG. 7 is a diagram for illustrating output characteristics of power-onreset circuit PORb.

Referring to FIG. 7, when externally supplied power supply voltage Vccincreases from 0 V to voltage VLb, the output of power-on reset circuitPORb is fixed at a low level. This output changes to a high levelrepresenting cancellation of reset, when power supply voltage Vcc is 2.6V±0.1 V. Namely, reset is cancelled when Vcc is in a range of 2.5 V to2.7 V. In voltage dividing circuit 54, band gap reference circuit BGR,and current source CS in FIG. 5, steady-state currents of 1 μA, 1 μA,and 0.2 μA flow, respectively. Thus, relative to power-on reset circuitPORa, although power-on reset circuit PORb has higher accuracy of thereset cancellation voltage, power-on reset circuit PORb accordingly haslarge steady-state current.

Regarding power-on reset circuit PORa, as compared with power-on resetcircuit PORb, a lower power supply voltage can cause the output ofpower-on reset circuit PORa to be fixed at the level which effectsreset, and therefore required steady-state current is also small. It istherefore desirable to configure the data processing device to take theadvantage of power-on reset circuit PORa (reset can be effected by arelatively lower power supply voltage and the steady-state current issmaller) and also take the advantage of power-on reset circuit PORb (thehigh accuracy of the reset cancellation voltage).

FIG. 8 is a block diagram showing main blocks of the data processingdevice. This block diagram will be used to explain a switching operationof the data processing device to the standby mode.

Referring to FIG. 8, before executing an instruction to make atransition to the standby mode (low power consumption state), centralprocessing unit CPU makes setting of registers in storage unit 28 sothat power-on reset circuit PORb is stopped and only power-on resetcircuit PORa operates upon transition to the standby mode (low powerconsumption state). Then, central processing unit CPU executes theinstruction to make a transition to the standby mode (low powerconsumption state). In response to this, system control unit SYSC refersto the relevant register in storage unit 28 to inactivate control signalSON and thereby stop low voltage detect circuit LVD and power-on resetcircuit PORb. As a result, in the standby mode (low power consumptionstate), it is only power-on reset circuit PORa that continues operating,among the components in voltage detection unit 10.

Likewise, system control unit SYSC also refers to the setting of therelevant register in storage unit 28 to instruct power supply circuit 24and clock circuit 26 to stop supplying the power supply voltage and tostop supplying the clock to central processing unit CPU, data transferunit DMAC, the memory, analogue-to-digital conversion unit ADC, andserial communication unit SCIO.

It should be noted that, since central processing unit CPU makes settingof the register before transition to the standby state, a user maychange the program to appropriately change the state of powerconsumption in the standby state.

FIG. 8 illustrates the example where system control unit SYSC isconfigured to be able to operate with a lower voltage than centralprocessing unit CPU and controls recovery from the standby mode (lowerpower consumption state). Alternatively, a control unit which isoperable with such a low voltage may be provided in power supply circuit24.

FIG. 9 is an operation waveform chart for illustrating a low powerconsumption period and an operation period.

Referring to FIGS. 8 and 9, in the standby mode (low power consumptionstate) before time t1, while power supply voltage Vcc which isexternally supplied from the battery is higher than detection voltageVrst (PORa) of power-on reset circuit PORa, power-on reset circuit PORacontinues monitoring the voltage level of the externally suppliedvoltage.

At time t1, in the case where data processing device 2 recovers from thestandby mode (low power consumption state) in response to a signal fromsensor 4 for example in FIG. 1 connected to the data processing device2, power-on reset circuit PORb also resumes its operation. Namely, evenif an instruction to stop power-on reset circuit PORb is written in arelevant register of storage unit 28 before transition to the standbymode (low power consumption state), the register is cleared in responseto output of reset signal NPORA and, in response to this, system controlunit SYSC activates signal SON and accordingly power-on reset circuitPORb starts operating.

At this time, if externally supplied power supply voltage Vcc is higherthan detection voltage Vrst (PORb), data processing device 2 can recoverfrom the standby mode (low power consumption state) to performprocessing on an externally input signal (operation period T1).

At the time like time t5, however, if externally supplied power supplyvoltage Vcc has decreased below detection voltage Vrst (PORb) at thetime when power-on reset circuit PORb resumes its operation, power-onreset circuit PORb outputs the reset signal (operation period T3). Atthis time, system control unit SYSC does not cancel reset. Accordingly,the accuracy of the reset cancellation voltage is maintained.

At the time like time t3, if externally supplied power supply voltageVcc decreases below detection voltage Vrst (PORa) during the standbymode (during low power consumption state), power-on reset circuit PORaoutputs reset signal NPORA. In response to output of reset signal NPORAor NPORB from power-on reset circuit PORa or power-on reset circuitPORb, data processing device 2 initializes the memory and register aswell as other circuits including a latch circuit in a hardware manner(namely by system control unit SYSC, not by software reset of the CPU),and waits for cancellation of the reset signal. At this time, even if aninstruction to stop is written in a relevant register of storage unit 28before transition to the standby mode (low power consumption state),power-on reset circuit PORb starts operating since the register iscleared in response to output of reset signal NPORA.

It should be noted that, system control unit SYSC is configured so thatthe lower limit of the operating power supply voltage is lower than thatof central processing unit CPU, and therefore can perform processing foractivating power-on reset circuit PORb in response to output of thereset signal of power-on reset circuit PORa.

At the time like time t3, in the case where externally supplied powersupply voltage Vcc supplied from the battery returns to a state higherthan detection voltage Vrst (PORa) immediately after the reset signal isoutput, power-on reset circuit PORa can output the reset cancellationsignal. Furthermore, in the case where externally supplied voltage Vccreturns to a state higher than detection voltage Vrst (PORb), power-onreset circuit PORb can also output the reset cancellation signal.Accordingly, reset of data processing device 2 is cancelled and dataprocessing device 2 can thus be rebooted.

At the time like time t3, when a temporary decrease of the voltageoccurs, an unexpected value is set at a latch circuit for example in thecircuitry of data processing device 2. The decrease of externallysupplied power supply voltage Vcc can be detected to perform the resetoperation and thereby prevent the operation of data processing device 2from becoming unstable.

In contrast, at the time like time t5, when data processing device 2recovers from the standby mode (low power consumption state) in responseto an externally input signal or output of the reset signal andexternally supplied power supply voltage Vcc at this time is lower thandetection voltage Vrst (PORb) or further lower than detection voltageVrst (PORa), one of or both power-on reset circuit PORa and power-onreset circuit PORb cannot output the reset cancellation signal. Sincesystem control unit SYSC does not cancel reset, data processing device 2continues stopping without cancellation of the reset (operation periodT3).

FIG. 10 is a flowchart for illustrating a process regarding a power-onreset operation performed by the data processing device.

Referring to FIG. 10, the data processing device is normally powered instep S1. In response to this, the data processing device performs thepower-on reset operation and thereafter enters an operation period instep S2. The power-on reset operation at this time is carried out whileboth power-on reset circuit PORa and power-on reset circuit PORb areactivated.

In step S2, data processing device 2 performs a data processingoperation in a normal mode in which the power-on reset is cancelled.This processing is processing of a control program to be performed inthis period as essential processing of the system. For example, in thecase of the electricity meter, this processing is recording of theamount of power consumption which is performed every 24 hours. In theoperation period of step S2, central processing unit CPU and otherperipheral circuits are started as required to operate.

When the operation in step S2 is completed, data processing device 2switches from the normal mode to the standby mode of the low powerconsumption state. In step S3, before switch to the standby mode,central processing unit CPU makes setting of registers in storage unit28 so that only power-on reset circuit PORa is used while power-on resetcircuit PORb is not used. In addition, as required, setting for stoppinglow voltage detect circuit LVD, power supply circuit 24, and clockcircuit 26 is also written in the relevant register in storage unit 28.

After this, in step S4, central processing unit CPU executes aninstruction to make transition to the standby mode of the low powerconsumption state. In step S5, system control unit SYSC refers to thesetting of the register in storage unit 28 and accordingly stopspower-on reset circuit PORb and low voltage detect circuit LVD and alsostops power supply circuit 24 and clock circuit 26. Thus, power-on resetcircuit PORb and low voltage detect circuit LVD are stopped to furtherreduce the power consumption in the standby mode as compared with theconventional system.

In step S6, system control unit SYSC waits for input of a trigger forrecovery from the standby mode (low power consumption state). Thetrigger for recovery from the standby mode (low power consumption state)may be a request to recover provided from communication unit 6 in FIG.1, interruption by timer 8, or the like. In step S6, when the triggerfor recovery is input, the process proceeds to step S10. When thetrigger for recovery is not input, the process proceeds to step S7.

In step S7, it is determined whether or not externally supplied powersupply voltage Vcc is lower than detection voltage Vrst (PORa) ofpower-on reset circuit PORa. Specifically, system control unit SYSCmakes this determination based on whether output NPORA of power-on resetcircuit PORa is the L level or not. In step S7, in the case whereexternally supplied power supply voltage Vcc has not decreased belowdetection voltage Vrst (PORa), the process returns to step S6 in whichdetection of whether or not a trigger for recovery is input iscontinued.

In step S7, in the case where the decrease of externally supplied powersupply voltage Vcc is detected, reset is executed in step S8, thesetting of the register in storage unit 28 is cleared, and the processproceeds to step S9. In step S9, like step S7, it is determined whetheror not externally supplied power supply voltage Vcc is lower thandetection voltage Vrst (PORa) of power-on reset circuit PORa.

In step S9, in the case where externally supplied power supply voltageVcc has not decreased below detection voltage Vrst (PORa) (in the casewhere the voltage has increased), the process proceeds to step S10. Incontrast, in the case where externally supplied power supply voltage Vccis still lower than detection voltage Vrst (PORa) in step S9, theprocess returns again to step S8 and reset is continued.

In step S10, system control unit SYSC activates control signal SON inFIG. 5 to turn on switch 52 and cause the power supply voltage to besupplied to circuit 70. Accordingly, power-on reset circuit PORb and lowvoltage detect circuit LVD start operating. Furthermore, the powersupply circuit and the clock circuit are also activated to startsupplying the power supply voltage and the clock signal.

Subsequently, in step S11, it is determined whether or not externallysupplied power supply voltage Vcc is lower than detection voltage Vrst(PORb) of power-on reset circuit PORb. Specifically, system control unitSYSC makes this determination based on whether or not output NPORB ofpower-on reset circuit PORb is the L level.

In step S11, in the case where externally supplied power supply voltageVcc is lower than detection voltage Vrst (PORb) of power-on resetcircuit PORb, reset is executed in step S12, the setting of the registerin storage unit 28 is cleared, and the process proceeds to step S13. Instep S13, like step S11, it is determined whether or not externallysupplied power supply voltage Vcc is lower than detection voltage Vrst(PORb) of power-on reset circuit PORb.

In step S13, in the case where externally supplied power supply voltageVcc is lower than detection voltage Vrst (PORb) of power-on resetcircuit PORb, step S12 is performed again and cancellation of reset iswaited for. If externally supplied power supply voltage Vcc continuesbeing lower than detection voltage Vrst (PORb) of power-on reset circuitPORb, reset is not cancelled as seen in period T3 of FIG. 9.

In step S13, in the case where externally supplied power supply voltageVcc has increased to be higher than detection voltage Vrst (PORb) ofpower-on reset circuit PORb, reset is cancelled and the process returnsto step S10.

In step S10, power-on reset circuit PORb and low voltage detect circuitLVD start operating, and the power supply circuit and the clock circuitare also activated to start supplying the power supply voltage and theclock signal. After this, in step S11, in the case where externallysupplied power supply voltage Vcc has not decreased below detectionvoltage Vrst (PORb) of power-on reset circuit PORb, the process proceedsto step S2 in which processing in the operation period of the dataprocessing device is performed.

The processing from step S9 to step S13 may be performed as a part ofthe processing for powering (step S1). In this case, if externallysupplied power supply voltage Vcc is lower than detection voltage Vrst(PORa) of power-on reset circuit PORa in step S9, the time is waited forat which externally supplied voltage Vcc increases (step S9 iscontinued).

With the above-described configuration, the amount of current necessaryin the period in which the data processing device is in the standby mode(low power consumption state) can be reduced. Accordingly, degradationof the current supply ability of the battery which supplies anexternally supplied voltage to the data processing device can belessened and consequently extension of the operating time of the systemas a whole can be achieved.

In addition, the power consumption of the whole system can also bereduced even if the power supply voltage is supplied not from thebattery but from a commercial power supply without decrease of itscurrent supply ability.

Finally, referring again to the drawings, an overview of the dataprocessing device of the present embodiment will be provided. As shownin FIGS. 2 and 8, data processing device 2 includes: first power-onreset circuit PORa shown in FIG. 4; second power-on reset circuit PORbshown in FIG. 5 with higher power consumption and higher reset voltageaccuracy than the first power-on reset circuit; storage unit 28 storinginformation for determining whether to keep second power-on resetcircuit PORb in an active state or an inactive state; and centralprocessing unit CPU initialized in response to respective outputs offirst and second power-on reset circuits PORa, PORb and setting theinformation in the storage unit 28.

Preferably, data processing device 2 has a normal mode and a standbymode. Central processing unit CPU sets the information in storage unit28 so that, in the standby mode, second power-on reset circuit PORb isinactivated while first power-on reset circuit PORa is used to detectthat a power supply voltage has decreased to a voltage which meets areset condition.

More preferably, prior to switch from the normal mode to the standbymode, central processing unit CPU sets the information in storage unit28 so that second power-on reset circuit PORb is inactivated, andthereafter switches to the standby mode.

Still more preferably, as shown in FIG. 8, data processing device 2further includes system control unit SYSC receiving respective outputsof first and second power-on reset circuits PORa, PORb. As describedwith reference to FIG. 10, in a case where the output of first power-onreset circuit PORa indicates reset and thereafter indicates cancellationof reset (NO in step S9) and second power-on reset circuit PORb isinactivated in the standby mode, system control unit SYSC activatessecond power-on reset circuit PORb (step S10) and, when the output ofsecond power-on reset circuit PORb indicates cancellation of reset (NOin step S13 and NO in step S11), system control unit SYSC cancels resetof central processing unit CPU.

Preferably, data processing device 2 has a normal mode and a standbymode. Central processing unit CPU can select one of use and non-use ofsecond power-on reset circuit PORb in the standby mode, by setting theinformation in storage unit 28 before switching from the normal mode tothe standby mode. Namely, while an example has been described inconnection with the embodiment where second power-on reset circuit PORbis not used during the standby mode, a program executed by centralprocessing unit CPU can be changed to thereby change the operation sothat second power-on reset circuit PORb is also used during the standbymode.

Preferably, as shown in FIG. 4, first power-on reset circuit PORaincludes inverter 48 having an input to which connected internal node N1charged to have an increased potential as potential of a power supplynode increases. As shown in FIG. 5, second power-on reset circuit PORbincludes comparison circuit 58 comparing an output of band gap referencecircuit BGR with an output of voltage dividing circuit 54 dividing avoltage of the power supply node.

It should be construed that embodiments disclosed herein are by way ofillustration in all respects, not by way of limitation. It is intendedthat the scope of the present invention is defined by claims, not by thedescription above, and encompasses all modifications and variationsequivalent in meaning and scope to the claims.

REFERENCE SIGNS LIST

1 data processing system; 2 data processing device; 4 sensor; 6communication unit; 8 timer; 10 voltage detection unit; 12 battery; 18printed circuit board; 21 bus; 22 memory; 24 power supply circuit; 26clock circuit; 28 storage unit; 42, 44 transistor; 46 capacitor; 48, 50inverter; 52 switch; 54 voltage dividing circuit; 56, 60 selector; 58,62 voltage comparator; 70 circuit; ADC analog-to-digital conversionunit; BGR band gap reference circuit; CPU central processing unit; CScurrent source; DMAC data transfer unit; INTC interrupt controller; LVDlow voltage detect circuit; PORa, PORb power-on reset circuit; SCIOserial communication unit; SYSC system control unit; VDC voltage downconverter circuit; VREFBUF reference voltage generation circuit

What is claimed is:
 1. A data processing device, comprising: a firstpower-on reset circuit; a second power-on reset circuit with a higherpower consumption and a higher reset voltage accuracy than said firstpower-on reset circuit; a low voltage detect circuit; a storage unitstoring information for determining whether to keep said second power-onreset circuit and said low voltage detect circuit in an active state oran inactive state; a central processing unit initialized in a responseto respective outputs of said first and second power-on reset circuitsand setting said information in said storage unit; and a power supplynode providing a power to the data processing device, wherein said firstpower-on reset circuit includes an internal node that is charged to havea variable potential as a potential of the power supply node changes,wherein the data processing device is configured to select one of afirst operation and a second operation in a standby mode, wherein, inthe first operation, said first power-on reset circuit with a lowerreset voltage is enabled, while said low voltage detect circuit and saidsecond power-on reset circuit are enabled, and wherein, in the secondoperation, said first power-on reset circuit with the lower resetvoltage is enabled, while said low voltage detect circuit and saidsecond power-on reset circuit are disabled.
 2. The data processingdevice according to claim 1, wherein said data processing device has anormal mode and said standby mode, and wherein said central processingunit sets said information in said storage unit so that, in said standbymode, said second power-on reset circuit and said low voltage detectcircuit are inactivated while said first power-on reset circuit is usedto detect that a power supply voltage has decreased to a voltage whichmeets a reset condition.
 3. The data processing device according toclaim 2, wherein, prior to switch from said normal mode to said standbymode, said central processing unit sets said information in said storageunit so that said second power-on reset circuit and said low voltagedetect circuit are inactivated, and thereafter switches to said standbymode.
 4. The data processing device according to claim 3, furthercomprising a control unit receiving respective outputs of said first andsecond power-on reset circuits, wherein, in a case where the output ofsaid first power-on reset circuit indicate a reset and thereafterindicates cancellation of the reset and said second power-on resetcircuit is inactivated in said standby mode, said control unit activatessaid second power-on reset circuit and, when the output of said secondpower-on reset circuit indicates cancellation of the reset, said controlunit cancels a reset of said central processing unit.
 5. The dataprocessing device according to claim 1, wherein said data processingdevice has a normal mode and said standby mode, and wherein said centralprocessing unit is configured to select one of use and non-use of saidsecond power-on reset circuit in said standby mode, by setting saidinformation in said storage unit before switching from said normal modeto said standby mode.
 6. The data processing device according to claim1, wherein said first power-on reset circuit further includes aninverter having an input to which is connected to the internal nodecharged to have an increased potential as the potential of the powersupply node increases, and wherein said second power-on reset circuitincludes a comparison circuit comparing an output of a band gapreference circuit with an output of a voltage dividing circuit dividinga voltage of the power supply node.
 7. A data processing system,comprising: a printed circuit board; and a data processing devicemounted on said printed circuit board, said data processing deviceincluding: a first power-on reset circuit; a second power-on resetcircuit with higher power consumption and higher reset voltage accuracythan said first power-on reset circuit; a low voltage detect circuit; astorage unit storing information for determining whether to keep saidsecond power-on reset circuit and said low voltage detect circuit in anactive state or an inactive state; a central processing unit initializedin a response to respective outputs of said first and second power-onreset circuits and setting said information in said storage unit; and apower supply node providing a power to the data processing device,wherein said first power-on reset circuit includes an internal node thatis charged to have a variable potential as a potential of the powersupply node changes, wherein said data processing device is configuredto select one of a first operation and a second operation in a standbymode, wherein, in the first operation, said first power-on reset circuitwith a lower reset voltage is enabled, while and said low voltage detectcircuit and said second power-on reset circuit are enabled, and wherein,in the second operation, said first power-on reset circuit with thelower reset voltage is enabled, while and said low voltage detectcircuit and said second power-on reset circuit are disabled.
 8. The dataprocessing system according to claim 7, wherein the internal node ischarged to have an increased potential as the potential of the powersupply node increases.
 9. The data processing system according to claim8, wherein said first power-on reset circuit further includes aninverter having an input connected to the internal node.
 10. The dataprocessing system according to claim 7, wherein said first power-onreset circuit further includes an inverter having an input connected tothe internal node.
 11. The data processing system according to claim 10,wherein said second power-on reset circuit includes a voltage dividingcircuit dividing a voltage of the power supply node.
 12. The dataprocessing system according to claim 11, wherein said second power-onreset circuit further includes a comparison circuit that receives adivided voltage of the voltage dividing circuit.
 13. The data processingsystem according to claim 7, wherein said second power-on reset circuitincludes a comparison circuit comparing an output of a band gapreference circuit with an output of a voltage dividing circuit dividinga voltage of the power supply node.
 14. The data processing systemaccording to claim 13, wherein said first power-on reset circuit furtherincludes an inverter having an input to which is connected the internalnode charged to have an increased potential as the potential of thepower supply node increases.
 15. The data processing device according toclaim 1, wherein the internal node is charged to have an increasedpotential as the potential of the power supply node increases.
 16. Thedata processing device according to claim 1, wherein said first power-onreset circuit further includes an inverter having an input connected tothe internal node.
 17. The data processing device according to claim 16,wherein the internal node is charged to have an increased potential asthe potential of the power supply node increases.
 18. The dataprocessing device according to claim 17, wherein said second power-onreset circuit includes: a voltage dividing circuit dividing a voltage ofthe power supply node; and a comparison circuit that received a dividedvoltage of the voltage dividing circuit.
 19. The data processing deviceaccording to claim 1, wherein said second power-on reset circuitincludes a comparison circuit comparing an output of a band gapreference circuit with an output of a voltage dividing circuit dividinga voltage of the power supply node.